One Document Analysis Hardware Software Interface (HSI)

Author: Leigh Brady, verification architect of Breker verification systems

HSI is a vital function that has now attracted the full attention of accelera pswg, and the lack of HSI has brought additional work to companies that want to adopt portable stimulus tools without some form of this function.

This blog series follows the requirements of accelera portable stimulus 1.0 standard (PSS), but we will be different in this specific blog. We will discuss the functionality of the first edition not included in the standard, namely hardware software interface (HSI). This is a vital feature that has now attracted the full attention of the accelera portable stimulation working group (pswg). The lack of it will bring extra work to companies that want to adopt portable stimulation tools without some form of this function.

This problem is most easily understood by considering the portability of testing. It refers to the ability to make a single description of the test intention and execute the test on various execution engines without modification. These execution engines include simulators, simulators, prototype solutions, virtual platforms and real chips running at the transaction level or register transfer level (RTL). Now consider a test that needs to get data to a register or memory location or retrieve the contents of that register or memory to ensure that the test runs correctly.

When executed on the simulator, it is easy to use the backdoor access mechanism without interfering with any aspect of the design under test (DUT). People using the universal verification method (UVM) will be familiar with the concepts of register abstraction layer (RAL) and backdoor memory access. When you retrieve the first chip from the Fab or try to migrate tests to drive the complete SOC on the simulator, you can rerun these tests. Using UVM, you usually need to completely rewrite the test tool.

This is usually not as easy as it sounds. Consider the case where the target is an emulator. You may have to run the necessary bus cycles to access memory and must operate without interfering with any circuits unrelated to that access. Some of these may not be obvious to users. The real purpose of portable stimulator is to solve this problem. However, version 1.0 does not solve this problem, so it is left to the reader for practice.

Although PSS can basically complete all operations that UVM can perform, PSS has other operation modes. It can generate tests that run on the processors included in the design for verification from the inside out. If you want to run tests on these processors, you either need some form of operating system to run on the processors, which will have a great impact on RTL tests, or you must treat them as bare metal processors. The last thing the validation team needs to do is spend a lot of time writing the necessary software to do this. HSI is a clean solution to this problem.

HSI provides basic OS like functions that allow tests to be written to standard APIs while hiding the mechanism for executing these tests. Whether you access the block register through the UVM sequence, or the register is contained in the embedded processor or the final chip, it makes the UVM register access look the same. For embedded processors, it can transfer the contents of the register to a location in memory that can be accessed externally, or feed the data through UART. For real silicon, registers can be accessed or modified through the scan chain. The mechanism for performing this function on each target is the same as the test writer. In most cases, this will be provided as part of the tools provided.

Hardware and software interfaces provide basic functions similar to the operating system, which allow tests to be written to standard APIs and hide the mechanism for executing these tests.

Of course, the tool can go further. Like a fully functional OS, it can schedule multiple tests and key resources across processor threads to really destroy SOC.

Although I should not discuss any details about the proposed solution with pswg, this function has existed in our previous tools for many years, and our customers are fully aware of the functions provided by this interface. Other tool vendors also run their own versions of the interface in their tools, but we hope accelera's efforts will lead to the unification of these interfaces.

As mentioned earlier, users of UVM will be very familiar with the concept of ral, which is necessary to enable the DUT and the test platform to agree on the general layout of bits in registers. Users of hardware / Software Co validation solutions will also be familiar with the need to define memory mapping - so that the test bench and design can be synchronized. Test suite synthesis knows the location of memory, any restrictions on it, and how processors and peripherals access it. For example, is the byte order small or large, or security restrictions associated with certain address ranges?

This is about the restrictions sought by the pswg on the PSS 1.1 release and does not contain all the contents required for a complete HSI. But this is a good start. Tool providers who truly understand the problem space and provide solutions that enable the implementation of a complete system level verification method go beyond these basics when providing HSI covering the entire bare metal layer.

Breker, vayavya, agnisys and other companies have been developing these solutions and know what it takes to make testing portable. These solutions improve the ability of PSS based test synthesis and reduce the efforts that users must make to obtain test portability. PSS reduces the risk of each supplier using its own language, but it does not eliminate the ability of each supplier to compete in the quality of the generated tests and the energy spent by users to generate them.

Editing: hfy

One Document Analysis Hardware Software Interface (HSI) 1

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