The Latest Achievements in the Improvement of Memory Chip Manufacturing Process of Changjiang Storag

Recently, the Changjiang storage process R & D team published the latest achievements in the improvement of memory chip manufacturing process at the 5th IEEE edtm. By exploring the formation mechanism of phosphorus doping process defects, it proposed and verified two surface treatment solutions, solved the problems existing in process manufacturing and improved the reliability of device manufacturing, It has laid a solid foundation for technology research and development to improve product quality.

Research background

In 3D NAND flash memory, oxide polysilicon oxide stack structure is the common source of the bottom layer of memory cell array. In order to obtain better electrical performance and lower interface roughness, LPCVD high concentration in-situ phosphorus doped amorphous silicon is the preferred process. However, when the doping concentration of phosphorus exceeds the solid solubility limit of silicon, most phosphorus will be in an unstable state and form surface deposition. In addition, in the oxide layer growth process, TEOS (tetraethyl orthosilicate: Si (OC2H5) 4) thermal decomposition is the simplest and lowest cost method, but there will be some incompletely reacted oxygen-containing groups on the oxide layer surface. In the process of film deposition, phosphorus and oxygen-containing groups on the surface will lead to abnormal growth of oxides, resulting in spherical bump defects, which will affect the subsequent process and even the function of the device.

In order to improve such process defects, the joint team of Changjiang storage and Institute of microelectronics of Chinese Academy of Sciences studied the formation mechanism of upper and lower interface defects of polysilicon in detail, and adopted wet cleaning to significantly reduce the number of bump defects at the two interfaces and greatly improve the yield.

Relevant achievements were presented at the 5th IEEE electron devices technology and manufacturing conference with "optimization of bump defect at high concentration in situ phosphorus doped polysilicon / TEOS oxide interface for 3D NAND flash memory application", with Zhao Dongxue as the first author, Xia Zhiliang and Huo Zongliang are co correspondents.

research contents

By studying the formation mechanism of bump defects at the interface between the upper and lower oxide layers, the team found that this is the result of the interaction between phosphorus and oxygen-containing groups on the interface. The team adopted two wet processes to remove phosphorus and oxygen-containing groups: Method 1 is applicable to the surface treatment of TEOS oxide layer. The treatment solution consists of S1 and S2. S1 is a hydroxyl rich solution, which can remove oxide groups without damaging the oxide layer; S2 is an alkaline solution, which can ensure the hydrophilicity of the silicon wafer surface to avoid watermark defects in the subsequent process; Method 2 is applicable to the surface treatment of amorphous silicon. The treatment chemical consists of S3 and S4. S3 solution is used to remove p205 impurities on the silicon surface; S4 is an oxidizing gas that prevents the formation of phosphorus deposition by re oxidation to form a dense film.

The results show that both methods can solve the interface defects between heavily phosphorus doped polysilicon and orthosilicate oxide, and the number of defects is significantly reduced after treatment.

Prospect

Through in-depth research on the manufacturing process defects of flash memory chips, the team explored the defect formation mechanism, proposed process solutions, achieved good improvement results in the verification, solved the problems existing in the process manufacturing, and improved the reliability of device manufacturing, which will become another booster for Changjiang storage to improve product quality. The technological breakthrough of Changjiang storage in the memory chip is not only the condensation of the sweat of thousands of people on the R & D and process side, but also the result of the joint cooperation between the upstream and downstream of the industrial chain. I wish the cooperation between the academic and industrial circles of integrated circuits can realize the landing of more products and help the rise of Chinese core.

Team Introduction

Huo Zongliang, CO chief technology officer of Changjiang storage, researcher and doctoral supervisor of the Research Office of nano processing and new device integration technology of Microelectronics Institute, now his research direction is new semiconductor storage technology. In 2003, he graduated from Peking University majoring in microelectronics, and later worked in Samsung Semiconductor R & D center.

Xia Zhiliang, head of process integration R & D Department of Changjiang storage technology center, doctoral supervisor and senior engineer of Microelectronics Institute. He graduated from Peking University in 2007 and later served as the chief engineer of Samsung Semiconductor Research Institute. His research direction is memory technology and device technology.

The Institute of microelectronics of the Chinese Academy of Sciences, formerly known as the former 109 factory of the Chinese Academy of Sciences, was established in 1958, merged with the Institute of semiconductor, computing technology and large scale integrated circuit of the Chinese Academy of Sciences in 1986, and officially changed its name to the Institute of microelectronics of the Chinese Academy of Sciences in September 2003. Microelectronics Institute is a comprehensive research and development institution with the most complete discipline layout in the field of microelectronics in China. It is the leading organization unit for forward-looking research and development of integrated circuit equipment and processes for major national science and technology projects. It is the supporting unit of the school of microelectronics of the University of Chinese Academy of Sciences and the preparatory supporting unit of the Institute of integrated circuit innovation of the Chinese Academy of Sciences.

Now it has 2 key laboratories of Chinese Academy of Sciences for basic research, 4 R & D centers for industry services, 5 R & D centers for industry applications and 4 R & D centers for core products.

Established in July 2016, Changjiang Storage Technology Co., Ltd. is an IDM integrated circuit enterprise focusing on the integration of 3D NAND flash memory design and manufacturing. With the support of the national science and technology major project 02, Changjiang storage and Microelectronics Institute has long-term production and research cooperation, independently developed the unique and innovative xtacking technology, successfully solved the technical problems of separation, processing and integration of storage array and read-write circuit, and achieved fruitful breakthroughs on the product side:

● at the end of 2017, Changshun launched the first self-designed 32-layer 3D NAND flash memory chip;

● in September 2019, 64 layer TLC 3D NAND flash memory chip equipped with xtacking independent architecture was officially mass produced;

The Latest Achievements in the Improvement of Memory Chip Manufacturing Process of Changjiang Storag 1

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